Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-108 Freescale Semiconductor
14.5.11.1 PCI Express EP Inbound Window Translation Address Register n
(PEX_EPIWTAR0–PEX_EPIWTAR3)
PEX_EPIWTAR0–PEX_EPIWTAR3, shown in Figure 14-132, contain the CSB address to be mapped for
a PCI Express inbound transaction hitting the respective BAR window. Inbound and outbound windows
for the same bus should not overlap. Therefore, situations where an inbound window translation points
back into an outbound window, or where an outbound translation window points back into an inbound
window, are not allowed.
Table 14-131 defines the bit fields of PEX_EPIWTARn.
14.5.12 PCI Express RC Inbound Address Mapping Registers
The registers discussed in this section control the inbound transactions attributes and address mapping
from the PCI Express bus to the CSB domain. These registers are used only in RC mode, and they serve
inbound transactions. When a PCI Express inbound transaction hits a valid address window defined by
these registers and the respective translation register is enabled, the incoming address is translated to a
CSB domain address and the transaction is forwarded to the CSB.
Offset 0xDE0, 0xDE4, 0xDE8, 0xDEC Access: Read/Write
31 12 11 1 0
R
TA — E N
W
Reset All zeros
Figure 14-132. PCI Express EP Inbound Window Translation Address Register n
(PEX_EPIWTAR0–PEX_EPIWTAR3)
Table 14-131. PEX_EPIWTARn Register Fields Description
Bits Name Description
31–12 TA Translation address. Contains the CSB base address to be mapped for a PCI Express inbound transaction
hitting the respective BAR window. The actual address is a concatenation of the TA field as most significant
bits and 12 zeroes as least significant bits {TA[31–12], 0x000}.
11–1 — Reserved
0 EN Enable. If set, indicates that the address mapping window is enabled.