Information
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-106 Freescale Semiconductor
Table 14-127 defines the bit fields of the PEX_OWBAR0–PEX_OWBAR3.
14.5.10.3 PCI Express Outbound Window Translation Address Register Low n
(PEX_OWTARL0–PEX_OWTARL3)
PEX_OWTARL0–PEX_OWTARL3, shown in Figure 14-130, contain the lower base address of the
PCI Express domain corresponding to this window. When this window is enabled and a CSB-based
transaction hits its base address register, the address is translated to a PCI Express address, according to
the PEX_OWTARLn and PEX_OWTARHn registers.
Table 14-128 defines the bit fields of PEX_OWTARLn.
14.5.10.4 PCI Express Outbound Window Translation Address Register High n
(PEX_OWTARH0–PEX_OWTARH3)
PEX_OWTARH0–PEX_OWTARH3, shown in Figure 14-131, contains the higher base address of the
PCI Express domain corresponding to this window. When this window is enabled and a CSB based
transaction hits its base address register, the address is translated to a PCI Express address according to the
Table 14-127. PEX_OWBARn Register Fields Description
Bits Name Description
31–12 BA Base address. The CSB window base address. Represents the CSB-based address for the window. The
actual address is a concatenation of the BAR field as most significant bits and 12 zeroes as least significant
bits {BA[31–12], 0x000}.
11–0 — Reserved. Must be zeros.
Offset 0xCA8, 0xCB8, 0xCC8, 0xCD8 Access: Read/Write
31 12 11 0
R
TAL —
W
Reset All zeros
Figure 14-130. PCI Express Outbound Window Translation Address Register Low n
(PEX_OWTARL0–PEX_OWTARL3)
Table 14-128. PEX_OWTARLn Register Fields Description
Bits Name Description
31–12 TAL Translation address low. The lower portion of the PCI Express address base. The actual address is a
concatenation of the TA field as most significant bits and 12 zeroes as least significant bits {TAL[31–12],
0x000}. The complete 64 bits address on the PCI Express bus is built of {PEX_OWTARH[TAH],
PEX_OWTARL[TAL], 0x000}.
11–0 — Reserved.