Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-105
NOTE
The access destination of the configuration access is decided in the address
converted with PEX_OWTARn if the TYPE field in PEX_OWARn is
configured for CFG[00].
14.5.10.2 PCI Express Outbound Window Base Address Register n
(PEX_OWBAR0–PEX_OWBAR3)
PEX_OWBAR0–PEX_OWBAR3, shown in Figure 14-129, contains the base address of the CSB window
for mapping to a PCI Express address. Note that the CSB base address must be aligned to 1 Kbyte. Inbound
and outbound windows for the same bus should not overlap. Therefore, situations where an inbound
window translation points back into an outbound window, or where an outbound translation window points
back into an inbound window, are not allowed.
7–5 TC Traffic class. Indicates the traffic class of the packet. Applicable only if user wants to send traffic using
multiple TC but single VC.
4 NSNP No snoop enable. When this bit and the PCI Express device control register [Enable No Snoop] bit are set,
the No Snoop bit for the packet is enabled. This attribute is not applicable and must be cleared for
configuration requests, I/O requests, and memory requests that are Message Signaled Interrupts.
0 PCI Express TLP snoop enabled
1 PCI Express TLP snoop disabled
3 RLXO Relax ordering enable. When this bit and the PCI Express device control register [Enable Relaxed] bit are
set, this bit enables the relaxed ordering bit for the packet. This applies only to memory transactions.
2–1 TYPE Window type. Indicates the type to which CSB transactions to the window address are mapped.
00 CFG
01 I/O
10 Memory
11 Reserved
0 EN Enable. Must be set to enable this window.
Offset 0xCA4, 0xCB4, 0xCC4, 0xCD4 Access: Read/Write
31 12 11 0
R
BA —
W
Reset All zeros
Figure 14-129. PCI Express Outbound Window Base Address Register n (PEX_OWBAR0–PEX_OWBAR3)
Table 14-126. PEX_OWAR0–PEX_OWAR3 Register Fields Description (continued)
Bits Name Description