Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-104 Freescale Semiconductor
14.5.10 PCI Express Outbound Address Mapping Registers
The registers discussed in this section control the outbound transactions attributes and address mapping
from the CSB domain to the PCI Express domain. These registers are used in both RC and EP modes, and
serve both PIO and DMA transactions.
14.5.10.1 PCI Express Outbound Window Attributes Register n
(PEX_OWAR0–PEX_OWAR3)
PEX_OWAR0–PEX_OWAR3, shown in Figure 14-128, sets the attributes for the respective address
window defined by the base and translation address registers for mapping of addresses related to CSB
outbound transactions to PCI Express addresses.
Table 14-126 defines the bit fields of the PEX_OWAR0–PEX_OWAR3.
1 PMETO Send PME Turn off message. This bit is valid only in RC mode and instructs the PCI Express controller to
send PME_Turn_Off message to downstream devices.
After setting this bit, the user must not try to transmit TLPs or initiate PME requests as the power may be
switched off.
This field is Write only. Read always returns zero.
0 IL2L3 Initiate L2/L3 entry. This bit is valid only in EP mode and instructs the PCI Express controller to transition
to L2/L3 ready state. This bit has to be asserted only after preparing for power removal.
After setting this bit, the user must not try to transmit TLPs or initiate PME requests as the power may be
switched off.
This field is Write only. Read always returns zero.
Offset 0xCA0, 0xCB0, 0xCC0, 0xCD0 Access: Read/Write
31 16
R
SIZE
W
Reset All zeros
15 1211 87 543210
R
SIZE — TC NSNP RLXO TYPE EN
W
Reset All zeros
Figure 14-128. PCI Express Outbound Window Attributes Register n (PEX_OWAR0–PEX_OWAR3)
Table 14-126. PEX_OWAR0–PEX_OWAR3 Register Fields Description
Bits Name Description
31–12 SIZE CSB window size. Indicates the size of window in bytes. The actual size is a concatenation of the SIZE field
as most significant bits and 12 zeroes as least significant bits {SIZE[31–12], 0x000}.
11–8 — Reserved. Must be zeros.
Table 14-125. PEX_PM_CTRL Register Fields Description (continued)
Bits Name Description