Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-103
14.5.9 PCI Express Power Management Registers
This section describes the PCI Express power management control register.
14.5.9.1 PCI Express Power Management Control Register (PEX_PM_CTRL)
This PCI Express PM Control Register shown in Figure 14-127, is used to control the link power
management by the PCI Express controller.
Table 14-125 defines the bit fields of the PEX_PM_CTRL.
Offset 0xC80 Access: Write Only
31 16
R
—
W
Reset All zeros
15 12 11 8 7 5 4 3 2 1 0
R
—
W PMESS EXL2 PMETO IL2L3
Reset All zeros
Figure 14-127. PCI Express PM Control Register (PEX_PM_CTRL)
Table 14-125. PEX_PM_CTRL Register Fields Description
Bits Name Description
31–4 — Reserved. Must be zeros.
3 PMESS PME Status Set. Set the PME Status bit in the PCI Express Power Management Status and Control
Register of the configuration space (Offset 0x048). In EP mode, this also causes the PCI Express controller
to send PM_PME message. PME message transmission is not supported in RC mode, but the PME status
bit can still be set.
PM PME message can be used to request for a device power state change. The message will be
transmitted only if PME is enabled and if PME Turn off message has not been received by the endpoint.
This field is Write only. Read always returns zero.
2 EXL2 Exit L2. This bit is valid only in RC mode and instructs the PCI Express controller to exit from L2/L3 ready
state and move to L0 active state so that traffic can be re-started on the PCI-Express link. This bit can be
set under the following conditions: the downstream device was shut down by the power manager (through
L2/L3 protocol) and later has its power restored, whereas the upstream device (CI Express controller as
RC) was in L2/L3 ready state (with power and clocks available).
This field is Write only. Read always returns zero.