Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-102 Freescale Semiconductor
20 PSCH Power state change. Indicates that a device power state change occurred. Change in Device power state
(D state) for function-0. D-state can transition between the supported values of D0, D1, D2 and D3-hot. PM
software changes D-state with a configuration write to PMCSR register in PM capability of the PCI Express.
The new D-state is available in the corresponding field of the PMCSR register. This bit must be cleared
after the interrupt is serviced.
19 EXL2L3 Exited L2/L3 state. Indication that the L2/L3 ready state has been exited and the current link state is L0.
Traffic can be re-started on the link. This bit is set when the link switches from the L2/L3 ready to L0 state
in response to an Exit L2 command. After issuing this command, the user must wait until the exited EXL2L3
bit is set before initiating traffic. This bit is valid only in RC mode. Setting this bit causes an interrupt to be
sent to CSB side. The bit must be cleared after the interrupt is serviced.
18 ENL2L3 Entered L2/L3 state. Indication to the Power manager that it is safe to switch off power to the downstream
device 100nsec after this bit is set. It is set when the PCI Express controller enters L2/L3 ready state. This
bit is valid only in RC mode. Setting this bit causes an interrupt to be sent to the CSB side. The bit must be
cleared after the interrupt is serviced.
17 PMETM
O
PME Turn Off Ack timeout event. Indication to power manager software that it is safe to switch off power to
the downstream device. It is set when the PCI Express controller detects that the timeout interval for
receiving a PME_To_Ack message from the downstream device has expired. This bit is valid only in RC
mode. This bit must be cleared after the interrupt is serviced.
16 RPMET
O
Received PME Turn off message. Notifies that main power to the device is to be removed. After this
notification is received, Uplink must not try to transmit TLPs or initiate PME requests because the power
may be switched off. After this message is received, the user should indicate the readiness to lose power
by setting the Initiate L2/L3 entry bit. This bit is valid only in EP mode. Setting this bit causes an interrupt
to be sent to the CSB side. The bit must be cleared after the interrupt is serviced.
15 ROF Receive overflow error. Indicates that the PCI Express reported a receive overflow error.
14 ECRC ECRC error. Indicates that a TLP received by the PCI Express failed the ECRC check.
13 PTLP Poisoned TLP. Indicates that a poisoned TLP was received by the PCI Express.
12 MFTLP Malformed TLP. Indicates that a malformed TLP was received by the PCI Express
11 CTO Completion timeout. Indicates that a PCI Express completion timeout occurred.
10 CA Completer abort. Indicates that a PCI Express completion Abort was received.
9 UR Unsupported request. Indicates that an unsupported request was received.
8 INTD PCI Express INTD. Indicates that an INTD interrupt was received on the PCI Express link. Valid for RC
applications only.
7 INTC PCI Express INTC. Indicates that an INTC interrupt was received on the PCI Express link. Valid for RC
applications only.
6 INTB PCI Express INTB. Indicates that an INTB interrupt was received on the PCI Express link. Valid for RC
applications only.
5 INTA PCI Express INTA. Indicates that an INTA interrupt was received on the PCI Express link. Valid for RC
applications only.
4–2 — Reserved
1 RST PCI Express reset. Indicates that a PCI Express reset occurred.
0 IMB Inbound mailbox ready. Indicates that the inbound mailbox control register ready bit (PEX_IMBCR[READY])
was set and the CSB host can read the mailbox data.
Table 14-124. PEX_CSMISR Register Fields Description (continued)
Bits Name Description