Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-101
Table 14-123 defines the bit fields of PEX_CSRDISR.
14.5.8.8 CSB System Miscellaneous Interrupt Status Register (PEX_CSMISR)
PEX_CSMISR, shown in Figure 14-126, maintains the status for interrupt issued to the CSB.
Table 14-124 defines the bit fields of PEX_CSMISR.
Table 14-123. PEX_CSRDISR Register Fields Description
Bits Name Description
31–17 — Reserved
16 RDA RDMA transfer aborted. Indicates that a Read DMA transaction was aborted.
15–9 — Reserved
8 RDS RDMA descriptor transfer completed. Indicates that a read DMA transaction corresponding to a descriptor
successfully completed.
7–1 — Reserved
0 RDC RDMA chain descriptor transfer completed. Indicates that a read DMA transaction corresponding to the last
descriptor in a chain successfully completed.
Offset 0xBFC Access: w1c
31 30 29 28 21 20 19 18 17 16
R
—
ERRD
—
PSCH
EXL2
L3
ENL2
L3
PMETO
RPM
ETO
W w1c w1c w1c w1c w1c w1c
Reset All zeros
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ROF ECRC PTLP MFTLP CTO CA UR INTD INTC INTB INTA
—
RST IMB
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 14-126. CSB System Miscellaneous Interrupt Status Register (PEX_CSMISR)
Table 14-124. PEX_CSMISR Register Fields Description
Bits Name Description
31–30 — Reserved
29 ERRD Error detected. Indicates that a PCI Express event occurred. The PCI Express event is reported by the
secondary status register (PCI Express secondary status register) at address 0x901E. Note that there is a
secondary mask, the PCI Express interrupt mask register (PEX_SS_INTR_MASK), at address 0x95A0.
Valid only for RC. This bit must be cleared after the interrupt is serviced and after the associated status
registers in the PCI Express controller causing the interrupt are cleared.
28–21 — Reserved