Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-100 Freescale Semiconductor
14.5.8.6 CSB System Write DMA Interrupt Status Register (PEX_CSWDISR)
PEX_CSWDISR, shown in Figure 14-124, maintains the status for interrupts issued to the CSB host
related to WDMA operation.
Table 14-122 defines the bit fields of PEX_CSWDISR.
14.5.8.7 CSB System Read DMA Interrupt Status Register (PEX_CSRDISR)
PEX_CSRDISR, shown in Figure 14-125, maintains the status for interrupts issued to the CSB host related
to the RDMA operation.
Offset 0xBF4 Access: w1c
31 17 16
R
—
WDA
W w1c
Reset All zeros
15 9 8 7 1 0
R
—
WDS
—
WDC
Ww1c w1c
Reset All zeros
Figure 14-124. CSB System Write DMA Interrupt Status Register (PEX_CSWDISR)
Table 14-122. PEX_CSWDISR Register Fields Description
Bits Name Description
31–17 — Reserved
16 WDA WDMA transfer aborted. Indicates that a write DMA transaction was aborted.
15–9 — Reserved
8 WDS WDMA descriptor transfer completed. Indicates that a write DMA transaction corresponding to a descriptor
successfully completed.
7–1 — Reserved
0 WDC WDMA chain descriptor transfer completed.Indicates that a write DMA transaction corresponding to the last
descriptor in a chain successfully completed.
Offset 0xBF8 Access: w1c
31 17 16
R
—
RDA
W w1c
Reset All zeros
15 9 8 7 1 0
R
—
RDS
—
RDC
Ww1c w1c
Reset All zeros
Figure 14-125. CSB System Read DMA Interrupt Status Register (PEX_CSRDISR)