Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-99
14.5.8.5 CSB System PIO Interrupt Status Register (PEX_CSPISR)
PEX_CSPISR, shown in Figure 14-123, maintains the status for interrupts issued to the CSB system host
related to PIO operation.
Table 14-121 defines the bit fields of PEX_CSPISR
Offset 0xBF0 Access: w1c
31 25 24 23 17 16
R
—
IPA
—
IPC
Ww1c w1c
Reset All zeros
15 9 8 1 0
R
—
OPA
—
OPC
Ww1c w1c
Reset All zeros
Figure 14-123. CSB System PIO Interrupt Status Register (PEX_CSPISR)
Table 14-121. PEX_CSPISR Register Fields Description
Bit Name Description
31–25 — Reserved
24 IPA Inbound PIO transaction aborted. Indicates that an inbound PCI Express PIO transaction was
aborted.
23–17 — Reserved
16 IPC Inbound PIO transaction completed. Indicates that an inbound PCI Express PIO transaction
was successfully completes.
15–9 — Reserved
8 OPA Outbound PIO transaction aborted. Indicates that an outbound PIO transaction was aborted.
7–1 — Reserved
0 OPC Outbound PIO transaction completed. Indicates that an outbound PIO transaction was
successfully completes.