Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-98 Freescale Semiconductor
17 PMETOIE PME to Ack timeout event interrupt enable. If set, enables the generation of an interrupt when a PME
to Ack timeout occurs. This bit is valid only in RC mode.
16 — Reserved
15 ROFIE Receive overflow error interrupt enable. If set, enables the generation of an interrupt when PCI
Express reports receive overflow error.
14 ECRCIE ECRC error interrupt enable. If set, enables the generation of an interrupt when a TLP is received by
PCI Express and it fails ECRC check.
13 PTLPIE Poisoned TLP interrupt enable. If set, enables the generation of an interrupt when a poisoned TLP
is received by PCI Express.
12 MFTLPIE Malformed TLP interrupt enable. If set, enables the generation of an interrupt when a malformed TLP
is received by PCI Express
11 CTOIE Completion timeout interrupt enable. If set, enables the generation of an interrupt when PCI Express
completion timeout occurs.
10 CAIE Completer abort interrupt enable. If set, enables the generation of an interrupt when PCI Express
completion Abort is received.
9 URIE Unsupported request interrupt enable. If set, enables the generation of an interrupt when an
unsupported request is received.
8 INTDIE PCI Express INTD interrupt enable. If set, enables the generation of an interrupt when an INTD
interrupt is received on the PCI Express link. Valid for RC applications only.
7 INTCIE PCI Express INTC interrupt enable. If set, enables the generation of an interrupt when an INTC
interrupt is received on the PCI Express link. Valid for RC applications only.
6 INTBIE PCI Express INTB interrupt enable. If set, enables the generation of an interrupt when an INTB
interrupt is received on the PCI Express link. Valid for RC applications only.
5 INTAIE PCI Express INTA interrupt enable. If set, enables the generation of an interrupt when an INTA
interrupt is received on the PCI Express link. Valid for RC applications only.
4–2 — Reserved
1 RSTIE PCI Express reset interrupt enable. If set, enables the generation of an interrupt when PCI Express
is reset.
0 IMBIE Inbound mailbox ready interrupt enable. If set, enables the generation of interrupt whenever the
inbound mailbox control register ready bit (PEX_IMBCR[READY]) is set.
Table 14-120. PEX_CSMIER Register Fields Description (continued)
Bit Name Description