Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-97
Table 14-119 defines the bit fields of PEX_CSRDIER.
14.5.8.4 CSB System Miscellaneous Interrupt Enable Register (PEX_CSMIER)
PEX_CSMIER, shown in Figure 14-122, controls the generation of interrupt to the CSB processor at
various events.
Table 14-120 defines the bit fields of PEX_CSMIER.
Table 14-119. PEX_CSRDIER Register Fields Description
Bit Name Description
31–17 Reserved
16 RDAIE RDMA transfer aborted interrupt enable. If set, enables the generation of interrupt for every Read
DMA transaction aborted.
15–9 Reserved.
8 RDSIE RDMA descriptor transfer completed interrupt enable. If set, enables the generation of an interrupt
when a Read DMA transactions corresponding to a descriptor complete successfully.
7–1 Reserved.
0 RDCIE RDMA chain descriptor transfer completed interrupt enable. If set, enables the generation of
interrupt when a Read DMA transactions for end-of-descriptor complete successfully.
Offset 0xBEC Access: Read/Write
31 30 29 28 21 20 19 18 17 16
R
ERRD
IE
PSCH
IE
PMETO
IE
W
Reset All zeros
151413 12111098765 4 3 2 1 0
R
ROF
IE
ECRC
IE
PTLP
IE
MFTLP
IE
CTO
IE
CAIE URIE
INTD
IE
INTC
IE
INTB
IE
INTA
IE
RSTIE IMBIE
W
Reset0 0 0 0 0000000 0 0 0 1 0
Figure 14-122. CSB System Miscellaneous Interrupt Enable Register (PEX_CSMIER)
Table 14-120. PEX_CSMIER Register Fields Description
Bit Name Description
31–30 Reserved
29 ERRDIE Error detected interrupt enable. If set, enables the generation of an interrupt when a PCI Express
event occurs. The PCI Express event is reported by the Secondary status register (PCI Express
Secondary Status Register) at address 0x901E. Note that a secondary mask exist by the PCI
Express PCI Interrupt Mask Register (PEX_SS_INTR_MASK) at address 0x95A0. Valid only for RC.
28–21 Reserved
20 PSCHIE Power state change interrupt enable. If set, enables the generation of an interrupt when a device
power state change occurs.
19–18 Reserved