Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-96 Freescale Semiconductor
Table 14-118 defines the bit fields of PEX_CSWDIER.
14.5.8.3 CSB System Read DMA Interrupt Enable Register (PEX_CSRDIER)
PEX_CSRDIER, shown in Figure 14-121, controls the generation of interrupt to the CSB system host at
various events during a RDMA operation.
Offset 0xBE4 Access: Read/Write
31 17 16
R
—WDAIE
W
Reset All zeros
15 9 8 7 1 0
R
—WDSIE— WDCIE
W
Reset All zeros
Figure 14-120. CSB System Write DMA Interrupt Enable Register (PEX_CSWDIER)
Table 14-118. PEX_CSWDIER Register Fields Description
Bit Name Description
31–17 — Reserved
16 WDAIE WDMA transfer aborted interrupt enable. If set, enables the generation of interrupt for every
DMA transaction aborted.
15–9 — Reserved
8 WDSIE WDMA descriptor transfer completed interrupt enable. If set, enables the generation of interrupt
when DMA transactions corresponding to a descriptor complete successfully.
7–1 — Reserved
0 WDCIE WDMA chain descriptor transfer completed interrupt enable. If set, enables the generation of
interrupt when DMA transactions for end-of-descriptor complete successfully.
Offset 0xBE8 Access: Read/Write
31 17 16
R
—RDAIE
W
Reset All zeros
15 9 8 7 1 0
R
— RDSIE — RDCIE
W
Reset All zeros
Figure 14-121. CSB System Read DMA Interrupt Enable Register (PEX_CSRDIER)