Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-95
Table 14-117 defines the bit fields of PEX_CSPIER.
14.5.8.2 CSB System Write DMA Interrupt Enable Register (PEX_CSWDIER)
PEX_CSWDIER, shown in Figure 14-120, controls the generation of interrupt to the CSB processor at
various events during a WDMA operation.
Offset 0xBE0 Access: Read/Write
31 25 24 23 17 16
R
— IPAIE —IPCIE
W
Reset All zeros
15 9 8 7 1 0
R
— OPAIE — OPCIE
W
Reset All zeros
Figure 14-119. CSB System PIO Interrupt Enable Register (PEX_CSPIER)
Table 14-117. PEX_CSPIER Register Fields Description
Bit Name Description
31–25 — Reserved
24 IPAIE Inbound PIO transaction aborted interrupt enable. If set, enables the generation of an interrupt
for every inbound PCI Express PIO transaction aborted.
23–17 — Reserved
16 IPCIE Inbound PIO transaction completed interrupt enable. If set, enables the generation of an
interrupt for every inbound PCI Express PIO transaction that successfully completes.
15–9 — Reserved
8 OPAIE Outbound PIO transaction abort interrupt enable. If set, enables the generation of an interrupt
for every outbound PIO transaction aborted.
7–1 — Reserved
0 OPCIE Outbound PIO transaction completed interrupt enable. If set, enables the generation of an
interrupt for every outbound PIO transaction that successfully completes.