Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-94 Freescale Semiconductor
Table 14-115 defines the bit fields of PEX_HRDIVR.
14.5.7.7 PCI Express Host Miscellaneous Interrupt Vector Register (PEX_HMIVR)
PEX_HMIVR, shown in Figure 14-118, contains the interrupt vector for mailbox message for MSI
interrupts issued to the PCI Express host. This includes CSB bridge reset and mailbox message.
Table 14-116 defines the bit fields of PEX_HMIVR.
14.5.8 CSB System Interrupt Registers
This section describes the registers for generating interrupts to the CSB system host (through the IPIC). It
consists of interrupt status registers and enable registers. Interrupts are generated only if the corresponding
enable bit is set, upon PIO, DMA and Miscellaneous events. The user has the flexibility of combining all
or partial interrupt signals to generate interrupts to the CSB system host.
14.5.8.1 CSB System PIO Interrupt Enable Register (PEX_CSPIER)
PEX_CSPIER, shown in Figure 14-119, controls the generation of interrupt to the CSB processor at
various events during an CSB or PCI Express PIO operation.
Table 14-115. PEX_HRDIVR Register Fields Description
Bit Name Description
31–5 — Reserved
4–0 IVEC Interrupt Vector. Contains the vector value for MSI.
Offset 0xBD8 Access: Read/Write
31 54 0
R
— IVEC
W
Reset All zeros
Figure 14-118. PCI Express Host Miscellaneous Interrupt Vector Register (PEX_HMIVR)
Table 14-116. PEX_HMIVR Register Fields Description
Bit Name Description
31–5 — Reserved
4–0 IVEC Interrupt Vector. Contains the vector value for MSI upon miscellaneous events.