Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-93
Table 14-113 defines the bit fields of PEX_HIPIVR.
14.5.7.5 PCI Express Host Write DMA Interrupt Vector Register (PEX_HWDIVR)
PEX_HWDIVR, shown in Figure 14-116, contains the interrupt vector for an MSI interrupt issued to the
PCI Express host upon WDMA events.
Table 14-114 defines the bit fields of PEX_HWDIVR.
14.5.7.6 PCI Express Host Read DMA Interrupt Vector Register (PEX_HRDIVR)
PEX_HRDIVR, shown in Figure 14-117, contains the RDMA interrupt vector for MSI interrupt issued to
the PCI Express host upon RDMA events.
Offset 0xBC0 Access: Read/Write
31 54 0
R
— IVEC
W
Reset All zeros
Figure 14-115. PCI Express Host Inbound PIO Interrupt Vector Register (PEX_HIPIVR)
Table 14-113. PEX_HIPIVR Register Fields Description
Bits Name Description
31–5 — Reserved
4–0 IVEC Interrupt vector. Contains the vector value for MSI.
Offset 0xBC8 Access: Read/Write
31 54 0
R
— IVEC
W
Reset All zeros
Figure 14-116. PCI Express Host Write DMA Interrupt Vector Register (PEX_HWDIVR)
Table 14-114. PEX_HWDIVR Register Fields Description
Bits Name Description
31–5 — Reserved
4–0 IVEC Interrupt vector. Contains the vector value for MSI.
Offset 0xBD0 Access: Read/Write
31 54 0
R
— IVEC
W
Reset All zeros
Figure 14-117. PCI Express Host Read DMA Interrupt Vector Register (PEX_HRDIVR)