Information

PCI Express Interface Controller

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

14-92 Freescale Semiconductor

14.5.7.3 PCI Express Host Outbound PIO Interrupt Vector Register

(PEX_HOPIVR)

PEX_HOPIVR, shown in Figure 14-114, contains the interrupt vector for MSI interrupt generation upon

an outbound PIO event. This vector is sent by the MSI interrupts to the PCI Express host if the interrupt is

enabled.

Table 14-112 defines the bit fields of PEX_HOPIVR.

14.5.7.4 PCI Express Host Inbound PIO Interrupt Vector Register (PEX_HIPIVR)

PEX_HIPIVR, shown in Figure 14-115, contains the interrupt vector for MSI interrupt generation upon an

inbound PIO event. This vectors will be sent by the MSI interrupts to the PCI Express host if the interrupt

is enabled.

4 WDC WDMA chain descriptor transfer completed. Hardware sets this bit when a write DMA transaction for the

last descriptor in a chain descriptor successfully completes.

3 IPA Inbound PIO transaction aborted. Hardware sets this bit when an inbound PCI Express PIO transaction

aborts.

2 IPC Inbound PIO transaction completed. Hardware sets this bit when an inbound PCI Express PIO transaction

successfully completes.

1 OPA Outbound PIO transaction aborted. Hardware sets this bit when an outbound PIO transaction aborts.

0 OPC Outbound PIO transaction completed. Hardware sets this bit when an outbound PIO transaction

successfully completes.

Offset 0xBA8 Access: Read/Write

31 54 0

— IVEC

Reset All zeros

Figure 14-114. PCI Express Host Outbound PIO Interrupt Vector Register (PEX_HOPIVR)

Table 14-112. PEX_HOPIVR Register Fields Description

Bits Name Description

31–5 — Reserved

4–0 IVEC Interrupt Vector. Contains the vector value for MSI.

Table 14-111. PEX_HISR Register Fields Description (continued)

Bits Name Description