Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 2-1
Chapter 2
Signal Descriptions
This chapter describes the external signals of the device. It is organized into the following sections:
• Overview of signals and cross references for signals that serve multiple functions, including a list
ordered by functional block.
• List of output signal states at reset
NOTE
A bar over a signal name indicates that the signal is active low, such as
MWE. Active-low signals are referred to as asserted (active) when they are
low and negated when they are high. Signals that are not active low, such as
TSEC1_RX_DV (interrupt input), are referred to as asserted when they are
high and negated when they are low.
2.1 Signals Overview
The signals are grouped as follows:
Figure 2-1 and Figure 2-2 show the external signals of the device and how the signals are grouped. Refer
to the MPC8308 PowerQUICC II Pro Processor Hardware Specification for a pinout diagram showing
pin numbers and a listing of all the electrical and mechanical specifications.
Note that individual chapters of this document provide details for each signal, describing each signal’s
behavior when asserted and negated and when the signal is an input or an output.
• DDR2 memory interface signals
• DUART interface signals
•I
2
C interface signals
• Ethernet management interface signals
• eTSEC1 and eTSEC2 interface signals
• PCI Express PHY signals
• Enhanced local bus interface signals
• GPIO interface signals
• Global timers/USB interface signals
• IPIC interface signals
• SPI interface signals
• JTAG interface signals
• System control signals
• Test interface signals
• Clock interface signals
• eSDHC interface signals
• Miscellaneous signals
• IEEE 1588 signals