Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-91
14.5.7.2 PCI Express Host Interrupt Status Register (PEX_HISR)
PEX_HISR, shown in Figure 14-113, maintains the status for interrupts issued to the PCI Express host.
Table 14-111 defines the bit fields of PEX_HISR.
3 IPAIE Inbound PIO transaction aborted interrupt enable. If set, enables the generation of an interrupt for every
inbound PCI Express PIO transaction aborted.
2 IPCIE Inbound PIO transaction completed interrupt enable. If set, enables the generation of an interrupt for every
inbound PCI Express PIO transaction that successfully completes.
1 OPAIE Outbound PIO transaction abort interrupt enable. If set, enables the generation of an interrupt for every
outbound PIO transaction aborted.
0 OPCIE Outbound PIO transaction completed interrupt enable. If set, enables the generation of an interrupt for
every outbound PIO transaction that successfully completes.
Offset 0xBA4 Access: w1c
31 16
R
—
W
Reset All zeros
15 12 11 10 9 8 7 6 5 4 3 2 1 0
R
—
CBR OMB RDA RDS RDC WDA WDS WDC IPA IPC OPA OPC
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 14-113. PCI Express Host Interrupt Status Register (PEX_HISR)
Table 14-111. PEX_HISR Register Fields Description
Bits Name Description
31–12 — Reserved
11 CBR CSB bridge reset. Hardware sets this bit upon a CSB bridge reset.
10 OMB Outbound mailbox ready. Hardware sets this bit when the outbound mailbox control register ready bit
(PEX_OMBCR[READY]) is set, indicating that the outbound mailbox is loaded with data to be read by the
PCI-Express host.
9 RDA RDMA transfer aborted. Hardware sets this bit when a read DMA transaction aborts.
8 RDS RDMA descriptor transfer completed. Hardware sets this bit when a read DMA transaction corresponding
to a descriptor successfully completes.
7 RDC RDMA chain descriptor transfer completed. Hardware sets this bit when a read DMA transaction for the last
descriptor in a chain descriptor successfully completes.
6 WDA WDMA transfer aborted. Hardware sets this bit when a write DMA transaction aborts.
5 WDS WDMA descriptor transfer completed. Hardware sets this bit when a write DMA transaction corresponding
to a descriptor successfully completes.
Table 14-110. PEX_HIER Register Fields Description (continued)
Bits Name Description