Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-90 Freescale Semiconductor
14.5.7 PCI Express Host Interrupt Registers
This section describes the registers for generating interrupts to the PCI Express host. It consists of interrupt
status registers and enable registers. Interrupts are generated only if the corresponding enable bit is set.
The device supports generation of MSI interrupts. Using these registers to generate interrupts to the
PCI Express host is applicable for only PCI Express EP applications.
14.5.7.1 PCI Express Host Interrupt Enable Register (PEX_HIER)
PEX_HIER, shown in Figure 14-112, enables the generation of interrupts to the PCI Express host at
various events during the CBS bridge, PIO and DMA operation.
Table 14-110 defines the bit fields of PEX_HIER.
Offset 0xBA0 Access: Read/Write
31 16
R
—
W
Reset All zeros
15 12 11 10 9 8 7 6 5 4 3 2 1 0
R
— CBRIE OMBIE RDAIE RDSIE RDCIE WDAIE WDSIE WDCIE IPAIE IPCIE OPAIE OPCIE
W
Reset All zeros
Figure 14-112. PCI Express Host Interrupt Enable Register (PEX_HIER)
Table 14-110. PEX_HIER Register Fields Description
Bits Name Description
31–12 — Reserved
11 CBRIE CSB bridge reset interrupt enable. If set, enables the generation of an interrupt upon a CSB bridge reset.
10 OMBIE Outbound mailbox ready interrupt enable. If set, enables the generation of interrupt when the outbound
mailbox control register ready bit (PEX_OMBCR[READY]) is set.
9 RDAIE RDMA transfer aborted interrupt enable. If set, enables the generation of interrupt for every Read DMA
transaction aborted.
8 RDSIE RDMA descriptor transfer completed interrupt enable. If set, enables the generation of an interrupt when a
read DMA transaction corresponding to a descriptor successfully completes.
7 RDCIE RDMA chain descriptor transfer completed interrupt enable. If set, enables the generation of interrupt when
a read DMA transaction for an end-of-descriptor successfully completes.
6 WDAIE WDMA transfer aborted interrupt enable. If set, enables the generation of interrupt for every DMA
transaction aborted.
5 WDSIE WDMA descriptor transfer completed interrupt enable. If set, enables the generation of interrupt when DMA
transactions corresponding to a descriptor successfully complete.
4 WDCIE WDMA chain descriptor transfer completed interrupt enable. If set, enables the generation of interrupt when
DMA transactions for end-of-descriptor successfully complete.