Information

PCI Express Interface Controller

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 14-89

14.5.6.3 PCI Express Inbound Mailbox Control Register (PEX_IMBCR)

PEX_IMBCR, shown in Figure 14-110, controls the generation of an interrupt to the local host indicating

that the PCI Express host has programmed the data mailbox register, and it is ready to be read. The CSB

host clears the bit after reading out the mailbox register. Note that setting the ready bit generates an

interrupt to the CSB host if enabled. The CSB host should clear the ready bit after reading the data mailbox

Table 14-108 defines the bit fields of PEX_IMBCR.

14.5.6.4 PCI Express Inbound Mailbox Data Register (PEX_IMBDR)

PEX_IMBDR, shown in Figure 14-111, contains the data to be read by the local CSB host.

Table 14-109 defines the bit fields of PEX_IMBDR.

Table 14-107. PEX_OMBDR Register Fields Description

Bits Name Description

31–0 MBD Mailbox Data. Contains the data to be read by the PCI Express host upon receiving an interrupt.

Offset 0xB60 Access: Read/Write

31 10

— READY

Reset All zeros

Figure 14-110. PCI Express Inbound Mailbox Control Register (PEX_IMBCR)

Table 14-108. PEX_IMBCR Register Fields Description

Bits Name Description

31–1 — Reserved

0 READY Inbound mailbox ready. If set, indicates that mailbox has valid data to be read by the CSB local host and

generates an interrupt if enabled.

Offset 0xB64 Access: Read/Write

31 0

MBD

Reset All zeros

Figure 14-111. PCI Express Inbound Mailbox Data Register (PEX_IMBDR)

Table 14-109. PEX_IMBDR Register Fields Description

Bits Name Description

31–0 MBD Mailbox data. Contains the data to be read by the CSB local host upon receiving an interrupt.