Information
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-87
Table 14-104 defines the bit fields of PEX_RDMA_ADDR.
14.5.5.6 PCI Express Read DMA Status Register (PEX_RDMA_STAT)
PEX_RDMA_STAT, shown in Figure 14-107, maintains the status of read DMA operations.
Table 14-105 defines the bit fields of PEX_RDMA_STAT.
Table 14-104. PEX_RDMA_ADDR Register Fields Description
Bits Name Description
31–0 FDSA First descriptor address. Indicates the address of the first descriptor on the CSB local memory (byte
swapped).
Offset 0xA48 Access: w1c
31 16
R
—
W
Reset All zeros
15 8765 4 3210
R
—
CPLER DAFER BRER DSUER
—
DSFER DSCPL CHCPL
W w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 14-107. PCI Express Read DMA Status Register (PEX_RDMA_STAT)
Table 14-105. PEX_RDMA_STAT Register Fields Description
Bits Name Description
31–8 — Reserved
7 CPLER PCI Express completion error. Hardware sets this bit to indicate that DMA operation cannot complete
successfully because of a PCI Express error.
6 DAFER DMA data write error. The hardware sets this bit to indicate an error during data write operation.
5 BRER Bridge error. Hardware sets this bit to indicate that DMA operation cannot complete successfully because
of a CSB bridge error.
4 DSUER Descriptor update error. Hardware sets this bit to indicate an error during descriptor update operation.
3 — Reserved
2 DSFER Descriptor fetch error. This bit is set by hardware to indicate that a descriptor read from the CSB has
terminated with an error.
1 DSCPL Descriptor DMA transfer completed. Hardware sets this bit after completing the transaction for the
descriptor.
0 CHCPL DMA chain transfer completed. Hardware sets this bit after completing the transaction in all the descriptors
that are currently programmed. This bit is set when DMA operation is complete and the DMA controller
encounters a NULL descriptor.
Note: When hardware sets this bit it is not guaranteed that the transferred data has fully reached its final
destination. Software should guarantee this another way.