Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-86 Freescale Semiconductor
14.5.5.4 PCI Express Read DMA Control Register (PEX_RDMA_CTRL)
PEX_RDMA_CTRL, shown in Figure 14-105, controls the RDMA operations.
Table 14-103 defines the bit fields of PEX_RDMA_CTRL.
14.5.5.5 PCI Express Read DMA First Address Register (PEX_RDMA_ADDR)
PEX_RDMA_ADDR, shown in Figure 14-106, contains the local memory address of the first descriptor.
Note that the content is byte swapped from a CSB native address.
Offset 0xA40 Access: Read/Write
31 16
R
—
W
Reset All zeros
15 11 10 9 8 2 1 0
R
— SNOOP RLXO — SUS START
W
Reset All zeros
Figure 14-105. PCI Express Read DMA Control Register (PEX_RDMA_CTRL)
Table 14-103. PEX_RDMA_CTRL Register Fields Description
Bits Name Description
31–11 — Reserved
10 SNOOP Snoop for write and read transactions to the descriptor. Controls the snooping of the e300 core
on the CSB bus to a transaction initiated by the RDMA. 0 Snoop disabled.
1 Snoop enabled.
9 RLXO Relaxed ordering for PCI Express. Indicates the relaxed ordering bit to be used for all PCI
Express transactions initiated by the DMA controller.
8–2 — Reserved
1 SUS DMA suspend. Software sets this bit to suspend the DMA controller.
0 START DMA start. Software can set this bit to indicate that a descriptor is ready and the DMA controller
can start transmission. Hardware resets this bit when a descriptor fetch cycle is initiated.
Offset 0xA44 Access: Read/Write
31 0
R
FDSA
W
Reset All zeros
Figure 14-106. PCI Express Read DMA First Address Register (PEX_RDMA_ADDR)