Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-85
Table 14-101 defines the bit fields of PEX_WDMA_ADDR.
14.5.5.3 PCI Express Write DMA Status Register (PEX_WDMA_STAT)
PEX_WDMA_STAT, shown in Figure 14-104, maintains the status of write DMA operations.
Table 14-102 defines the bit fields of PEX_WDMA_STAT.
Table 14-101. PEX_WDMA_ADDR Register Fields Description
Bit Name Description
31–0 FDSA First descriptor address. Indicates the address of the first descriptor on the CSB local
memory (byte-swapped).
Offset 0x9A8 Access: w1c
31 16
R
—
W
Reset All zeros
15 765 43210
R
—
DAFER BRER DSUER
—
DSFER DSCPL CHCPL
W w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 14-104. PCI Express Write DMA Status Register (PEX_WDMA_STAT)
Table 14-102. PEX_WDMA_STAT Register Fields Description
Bit Name Description
31–7 — Reserved
6 DAFER DMA data fetch error. Hardware sets this bit to indicate an error during the data fetch operation.
5 BRER Bridge error. Hardware sets this bit to indicate that DMA operation cannot complete successfully
because of a CSB bridge error.
4 DSUER Descriptor update error. Hardware sets this bit to indicate an error during descriptor update
operation.
3—Reserved
2 DSFER Descriptor fetch error. This bit is set by hardware to indicate that a descriptor read from the CSB
has terminated with an error.
1 DSCPL Descriptor DMA transfer completed. Hardware sets this bit after completing the transaction for the
descriptor.
0 CHCPL DMA chain transfer completed. Hardware sets this bit after completing the transaction in all the
descriptors that are currently programmed. This bit is set when DMA operation is complete and
the DMA controller encounters a NULL descriptor.
Note: When hardware sets this bit it is not guaranteed that the transferred data has fully reached
its final destination. Software should guarantee this another way. For additional information
see the PEX2 erratum in the errata document of the device.