Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-84 Freescale Semiconductor
14.5.5.1 PCI Express Write DMA Control Register (PEX_WDMA_CTRL)
PEX_WDMA_CTRL, shown in Figure 14-102, controls the WDMA operations.
Table 14-100 defines the bit fields of PEX_WDMA_CTRL.
14.5.5.2 PCI Express Write DMA First Address Register (PEX_WDMA_ADDR)
PEX_WDMA_ADDR, shown in Figure 14-103, contains the CSB local memory address of the first
descriptor. Note that the content is byte swapped from a CSB native address.
Offset 0x9A0 Access: Read/Write
31 16
R
—
W
Reset All zeros
15 11 10 9 8 5 4 2 1 0
R
— SNOOP RLXO TC SUS START
W
Reset All zeros
Figure 14-102. PCI Express Write DMA Control Register (PEX_WDMA_CTRL)
Table 14-100. PEX_WDMA_CTRL Register Fields Description
Bit Name Description
31–11 — Reserved
10 SNOOP Snoop for write and read transactions to the descriptor. Controls the snooping of the e300 core on
the CSB bus to a transaction initiated by the WDMA.
0 Snoop disabled.
1 Snoop enabled.
9 RLXO Relaxed ordering for PCI Express. Indicates the relaxed ordering bit to be used for all PCI Express
transactions initiated by the DMA controller.
8–5 — Reserved.
4–2 TC Traffic Class. Indicates the traffic class value to be used for TLP generation corresponding to the
traffic generated by the DMA.
1 SUS DMA suspend. Software sets this bit to suspend the DMA controller.
0 START DMA start. Software should set this bit to indicate that a descriptor is ready and the DMA controller
can start transmission. Hardware resets this bit when the descriptor fetch cycle is initiated.
Offset 0x9A4 Access: Read/Write
31 0
R
FDSA
W
Reset All zeros
Figure 14-103. PCI Express Write DMA First Address Register (PEX_WDMA_ADDR)