Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-83
14.5.4.2 PCI Express Inbound PIO Status Register (PEX_CSB_IBSTAT)
PEX_CSB_IBSTAT, shown in Figure 14-101, maintains the status of PCI Express Inbound PIO operations
through the PCI Express CSB bridge.
Table 14-99 defines the bit fields for PEX_CSB_IBSTAT.
14.5.5 DMA Registers
This section describes the following registers:
• Section 14.5.5.1, “PCI Express Write DMA Control Register (PEX_WDMA_CTRL)”
• Section 14.5.5.2, “PCI Express Write DMA First Address Register (PEX_WDMA_ADDR)”
• Section 14.5.5.3, “PCI Express Write DMA Status Register (PEX_WDMA_STAT)”
• Section 14.5.5.4, “PCI Express Read DMA Control Register (PEX_RDMA_CTRL)”
• Section 14.5.5.5, “PCI Express Read DMA First Address Register (PEX_RDMA_ADDR)”
• Section 14.5.5.6, “PCI Express Read DMA Status Register (PEX_RDMA_STAT)”
Offset 0x8E4 Access: w1c
31 16
R
—
W
Reset All zeros
15 3210
R
—
CSBER BRGER BENER
W w1c w1c w1c
Reset All zeros
Figure 14-101. PCI Express Inbound PIO Status Register (PEX_CSB_IBSTAT)
Table 14-99. PEX_CSB_IBSTAT Register Fields Description
Bit Name Description
31–3 — Reserved
2 CSBER CSB Bus Error. Hardware sets this bit to indicate that a CSB transaction bus error was encountered
during an inbound PIO operation.
1 BRGER CSB Bridge Error. Hardware sets this bit to indicate that an inbound PIO operation cannot complete
successfully because of a CSB bridge error.
0 BENER Bridge enable error. Hardware sets this bit to indicate that the an inbound PIO operation cannot complete
successfully because the CSB bridge inbound PIO operation is not enabled.