Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-82 Freescale Semiconductor
14.5.4 PCI Express Inbound PIO Registers
The registers discussed in this section control PIO inbound transactions initiated by a PCI Express device.
14.5.4.1 PCI Express Inbound PIO Control Register (PEX_CSB_IBCTRL)
PEX_CSB_IBCTRL, shown in Figure 14-100, controls the PCI Express inbound PIO operations.
Table 14-98 defines the bit fields for PEX_CSB_IBCTRL.
2 CSBER CSB Bridge error. Hardware sets this bit to indicate that an error has occurred during a PIO
outbound access to the CSB bridge by a CSB master.
1 BMPER Bridge mapping error. Hardware sets this bit to indicate that an outbound PIO operation could
not be completed successfully because a CSB bridge address mapping error has occurred.
0 BENER Bridge enable error.Hardware sets this bit to indicate that the an outbound PIO operation
could not be completed successfully because the CSB bridge outbound PIO operation was
not enabled.
Offset 0x8E0 Access: Read/Write
31 10
R
—PIOE
W
Reset All zeros
Figure 14-100. PCI Express Inbound PIO Control Register (PEX_CSB_IBCTRL)
Table 14-98. PEX_CSB_IBCTRL Register Fields Description
Bit Name Description
31–1 — Reserved
0 PIOE PIO enable. Must be set to enable an inbound PIO transaction. This field controls the general
enable of the PCI Express CSB bridge inbound PIO operation.
Table 14-97. PEX_CSB_OBSTAT Register Fields Description (continued)
Bit Name Description