Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-81
Table 14-96 defines the bit fields for PEX_CSB_OBCTRL.
14.5.3.2 PCI Express Outbound PIO Status Register (PEX_CSB_OBSTAT)
PEX_CSB_OBSTAT, shown in Figure 14-99, maintains the status of the CSB PIO operations through the
CSB slave controller. This register is replicated for each CSB PIO engine implemented.
Table 14-97 defines the bit fields for PEX_CSB_OBSTAT.
Table 14-96. PEX_CSB_OBCTRL Register Fields Description
Bits Name Description
31–10 — Reserved
9–7 TC Traffic class. Indicates TC value to be used for TLP generation corresponding to traffic received by the
CSB slave.
6–4 — Reserved
3 CFGWE Configuration window enable. Must be set to enable an outbound configuration transaction. Indicates that
a CSB transactions directed to an outbound window can be mapped to Config write and read TLPs and
transmitted to the PCI Express link.
2 IOWE I/O window enable. Must be set to enable an outbound I/O transaction. Indicates that a CSB transactions
directed to an outbound window can be mapped to I/O write and read TLPs and transmitted to the
PCI Express link.
1 MEMWE Memory window enable. Must be set to enable an outbound Memory transaction. Indicates that a CSB
transactions directed to an outbound window can be mapped to Memory write and read TLPs and
transmitted to the PCI Express link.
0 PIOE PIO enable. Must be set to enable an outbound PIO transaction. This field controls the general enable of
the PCI Express CSB bridge outbound PIO operation and should be set together with the other window
enable fields in this register.
Offset 0x844 Access: w1c
31 16
R
—
W
Reset All zeros
15 43210
R
—
PEXER CSBER BMPER BENER
W w1c w1c w1c w1c
Reset All zeros
Figure 14-99. PCI Express Outbound PIO Status Register (PEX_CSB_OBSTAT)
Table 14-97. PEX_CSB_OBSTAT Register Fields Description
Bit Name Description
31–4 — Reserved
3 PEXER PCI Express error. Hardware sets this bit to indicate that an outbound PIO operation could
not be completed successfully because there was an error in PCI Express completion
received.