Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-80 Freescale Semiconductor
Table 14-95 defines the bit field for PEX_CSB_STAT.
14.5.3 PCI Express Outbound PIO Registers
The registers discussed in this section control PIO outbound transactions initiated by a CSB master.
14.5.3.1 PCI Express Outbound PIO Control Register (PEX_CSB_OBCTRL)
PEX_CSB_OBCTRL, shown in Figure 14-98, controls the PCI Express Outbound PIO operations.
Table 14-95. PEX_CSB_STAT Register Fields Description
Bits Name Description
31–25 — Reserved
24 RDMARP Read DMA read transaction pending. Indicates whether a response is pending from the PCI Express
bus to a transfer by the read DMA engine.
0 No response pending
1 Response is pending
23–17 — Reserved
16 WDMARP Write DMA read transaction pending.Indicates whether a response is pending from the CSB bus to a
transfer from the write DMA engine.
0 No response pending
1 Response is pending
15–9 — Reserved
8 IBPIORP PCI Express inbound PIO read transaction pending. Indicates whether a response is pending from the
CSB bus for an inbound transfer from the PCI Express bus
0 No response pending
1 Response is pending
7–1 — Reserved
0 OBPIORP PCI Express outbound PIO read transaction pending. Indicates whether a response is pending from the
PCI Express bus for a transfer initiated on the CSB bus.
0 No response pending
1 Response is pending
Offset 0x840 Access: Read/Write
31 16
R
—
W
Reset All zeros
15 10 9 8 7 6 4 3 2 1 0
R
—TC—CFGWEIOWEMEMWEPIOE
W
Reset All zeros
Figure 14-98. PCI Express Outbound PIO Control Register (PEX_CSB_OBCTRL)