Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-79
14.5.2.2 PCI Express DMA Descriptor Timer Register (PEX_DMA_DSTMR)
PEX_DMA_DSTMR, shown in Figure 14-96, contains the timer value the DMA engine should wait for
before reading the next descriptor once it encounters a descriptor that is not ready. The timer should be
programmed to allow sufficient number of clocks before the DMA tries to fetch the descriptors again.
Table 14-94 defines the bit field for PEX_DMA_DSTMR.
14.5.2.3 PCI Express CSB Bridge Status Register (PEX_CSB_STAT)
PEX_CSB_STAT, shown in Figure 14-97, maintains the activity status of the DMA and PIO transactions.
When a transaction is initiated by the PCI Express DMA or PIO, the corresponding pending bit is set until
a response is received.
Offset 0x814 Access: Read/Write
31 0
R
DSRT
W
Reset All zeros
Figure 14-96. PCI Express DMA Descriptor Timer Register (PEX_DMA_DSTMR)
Table 14-94. PEX_DMA_DSTMR Fields Description
Bits Name Description
31–0 DSRT Descriptor ready timer. Represents the number of CSB bridge clocks that the DMA engine
should wait before checking whether the next descriptor is ready when it encounters invalid
descriptor.
Offset 0x81C Access: Read only
31 25 24 23 17 16
R
—
RDMARP
—
WDMARP
W
Reset All zeros
15 987 1 0
R
—
IBPIORP
—
OBPIORP
W
Reset All zeros
Figure 14-97. PCI Express CSB Bridge Status Register (PEX_CSB_STAT)