Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-78 Freescale Semiconductor
14.5.2.1 PCI Express CSB Bridge Control Register (PEX_CSB_CTRL)
PEX_CSB_CTRL, shown in Figure 14-95, controls the operation of the PCI Express to CSB bridge.
Table 14-93 defines the bit fields of PEX_CSB_CTRL.
Offset 0x808 Access: Read/Write
31 16
R
—
W
Reset000000 0 0 0 0 0 0 0 0 0 0
15 10 9 8 7 4 3 2 1 0
R
— DSAD — RDMAE WDMAE IBPIOE OBPIOE
W
Reset000000 0 1 0 0 1 1 0 0 0 0
Figure 14-95. PCI Express CSB Bridge Control Register (PEX_CSB_CTRL)
Table 14-93. PEX_CSB_CTRL Register Fields Description
Bits Name Description
31–10 — Reserved
9–8 DSAD Depth of descriptors array. Indicates the number of descriptors that should be placed at a
contiguous addresses block. The PCI Express controller DMA uses this information to fetch each
block of descriptors by a burst transaction. The implicit address of the next descriptor is the next
memory location. The last descriptor in the contiguous block contains the explicit address pointer
of the next set of descriptors. See Section 14.8.4, “Descriptor-Based DMA,” for detailed description.
Note that for most usages this field should be programmed to 00.
00 1—Single fetch descriptor chain mode. Each descriptor explicitly contains the address of the
next descriptor.
01 2—Burst fetch descriptor chain mode. The PCI Express controller will fetch two contiguous
descriptors in a burst.
10 4—Burst fetch descriptor chain mode. The PCI Express controller will fetch four contiguous
descriptors in a burst.
11 Reserved
7–4 — Reserved
3 RDMAE Read DMA enable. Must be set to enable the read DMA operation.
2 WDMAE Write DMA enable. Must be set to enable the write DMA operation.
1 IBPIOE Inbound PIO enable. Must be set to enable the PCI Express Inbound PIO operation.
0 OBPIOE Outbound PIO enable.Must be set to enable the PCI Express outbound PIO operation.