Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-77
Read DMA engines, a message manager and a set of configuration registers. Note that programming errors
may result in undefined behavior.
14.5.1 PCI Express CSB Bridge Configuration Space
The PCI Express CSB Bridge contains configuration registers for controlling and monitoring the
PCI Express and CSB related operations.
The various features supported are as follows:
• ATMU configuration
• PIO transactions control
• Write DMA engine control
• Read DMA engine control
• Mailbox
• Message signaled interrupts (MSI) generation
• Events monitoring
NOTE
The registers described in this section use little-endian byte ordering.
Software running on the local processor in big-endian mode must byte-swap
the data. No byte swapping occurs when the registers are accessed from the
PCI bus.
14.5.2 Global Registers
This section describes the following:
• Section 14.5.2.1, “PCI Express CSB Bridge Control Register (PEX_CSB_CTRL)”
• Section 14.5.2.2, “PCI Express DMA Descriptor Timer Register (PEX_DMA_DSTMR)”
• Section 14.5.2.3, “PCI Express CSB Bridge Status Register (PEX_CSB_STAT)”