Information
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-76 Freescale Semiconductor
14.4.8.3 Secondary Status Interrupt Mask Register (PEX_SS_INTR_MASK)
(RC Mode Only)
PEX_SS_INTR_MASK, shown in Figure 14-94, can be used to disable sideband interrupt generation
when error bits in the PCI Express secondary status register are set. See Section 14.4.3.7, “PCI Express
Secondary Status Register (RC Mode Only).” By default, interrupt generation due to secondary status
errors is disabled.
The fields of the PEX_SS_INTR_MASK are described in Table 14-92.
14.5 PCI Express CSB Bridge
The CSB bridge serve as an interface between the PCI Express core and the CSB domain. It controls the
transfer of the transactions between the PCI Express transaction layer and the CSB, and include Write and
1 L2L3RDY Entered L2/L3 ready state. This bit is set by hardware when the current power management
state is L2/L3 Ready. 100nsec after this bit is set, it is safe for the Power manager to switch off the
power of the downstream device. Once set, this bit will remain set, till software clears it by writing
1’b1 to this bit.
0 PTACKMR PME_To_Ack message received. This bit is set by hardware when PME_To_Ack message is
received by the Root Port from the downstream device. When this bit is set, it is safe for the Power
manager to switch off the power of the downstream device. Once set, this bit will remain set, till
software clears it by writing 1’b1 to this bit.
Offset 0x5A0 (RC mode only) Access: Mixed
31 65 4 3 2 1 0
R — M_DPE M_SSE M_RMA M_RTA M_STA M_MDPE
W
Reset 0 000000000000000000000000 0 1 1 1 1 1 1
Figure 14-94. PCI Express PCI Interrupt Mask Register (PEX_SS_INTR_MASK)
Table 14-92. PEX_SS_INTR_MASK Fields Description
Bits Name Description
31–6 — Reserved
5 M_DPE Mask detected parity error
4 M_SSE Mask signaled system error
3 M_RMA Mask received master abort
2 M_RTA Mask received target abort
1 M_STA Mask signaled target abort
0 M_MDPE Mask master data parity error
Table 14-91. PEX_PME_TO_ACK_SR Fields Description (continued)
Bits Name Description