Information
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-75
The fields of the PEX_PME_TO_ACK_TOR are described in Table 14-90.
14.4.8.2 PME_To_Ack Status Register (RC Mode Only)
The PME_To_Ack Status Register (PEX_PME_TO_ACK_SR) shown in Figure 14-93, can be used by the
power manager software to decide whether it is safe to switch off power to downstream devices, after
PME_Turn_Off message has been broadcast by the root port.
The fields of the PEX_PME_TO_ACK_SR are described in Table 14-91.
Offset 0x590 (RC mode only) Access: Mixed
31 22 21 0
R —
PME_TO_ACK_TIMEOUT
W
Reset00000000000110010101010001100000
Figure 14-92. PCI Express PME_To_Ack Timeout Register (PEX_PME_TO_ACK_TOR)
Table 14-90. PEX_PME_TO_ACK_TOR Fields Description
Bits Name Description
31–22 — Reserved
21–0 PME_TO_ACK_
TIMEOUT
After the RC broadcasts a PME_Turn_Off message, the power management module waits for the
duration of the PME_To_Ack timeout interval to receive a PME_To_Ack message from the
downstream device. If the Ack message is not received within this interval, the power manager
indicates that it is safe to switch off power because a timeout has occurred.
The value is calculated as:
Time (in µsec) × PCI Express controller core clock frequency (in MHz)
The recommended timeout duration is 1 msec to 10 msec to make sure that the downstream
devices get enough time to prepare for power-off condition.
Offset 0x594 Access: w1c
31 32 1 0
R
—
PTACKTO L2L3RDY PTACKMR
W w1c w1c w1c
Reset All zeros
Figure 14-93. PME_To_Ack Status Register (PEX_PME_TO_ACK_SR)
Table 14-91. PEX_PME_TO_ACK_SR Fields Description
Bits Name Description
31–3 — Reserved
2 PTACKTO PME_To_Ack timeout occurred. This bit is set by the hardware when PME_To_Ack message is not
received by the Root Port from downstream device within the timeout duration indicated by
PME_To_ACk_timeout register. When this bit is set, it is safe for the Power manager to switch off
the power of the downstream device. Once set, this bit will remain set, till software clears it by writing
1’b1 to this bit.