Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-73
The fields of the PEX_BAR_SIZEL register are described in Table 14-87.
14.4.7.2 PCI Express BAR Select Configuration Register (PEX_BAR_SEL)
PEX_BAR_SEL, shown in Figure 14-90, is used to select the specific BAR for which the size is being
configured by the PEX_BAR_SIZEL register. This register should be programmed before the
PEX_BAR_SIZEL register is accessed, and it is used only in EP mode.
Offset 0x4D8 Access: Mixed
31 12 11 0
R
MASK —
W
Reset11111100000000000000000000000000
Figure 14-89. PCI Express BAR Size Low Configuration Register (PEX_BAR_SIZEL)
Table 14-87. PEX_BAR_SIZEL Fields Description
Bits Name Description
31–12 MASK Mask. Sets the mask for the BAR, and any bit with a value of zero is masked. When the RC does
a configuration write to the BAR during the enumeration sequence, bits that are masked cannot
be modified and remain zeros. All ones and zeros in this register must be consecutive. The actual
size is according to the location of the least significant bit in the MASK[31–12] field, which is set.
If MASK[31–m] is all ones, the size is 2
m
bytes. If MASK[31–12] is all zeros, the window size is 4
Gigabytes. For example:
1111...1111 - 2
12
, 4 Kilobytes window.
1111...1110 - 2
13
, 8 Kilobytes window.
...
1100...0000 - 2
30
, 1 Gigabytes window.
1000...0000 - 2
31
, 2Gigabytes window.
0000...0000 - 4 Gigabytes window.
11–0 — Reserved. Must be zeros
Offset 0x4E0 Access: Mixed
31 210
R
—SEL
W
Reset00000000000000000000010000000000
Figure 14-90. PCI Express BAR Select Configuration Register (PEX_BAR_SEL)