Information

PCI Express Interface Controller

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

14-72 Freescale Semiconductor

external host reads the correct capability advertisements during enumeration, the CFG_READY bit in this

The fields of the PCI Express configuration ready register are described in Table 14-86.

14.4.7 PCI Express BAR Configuration Registers (EP Mode)

The registers described in this section configure the size and the prefetchable attributes of the base address

registers (BAR) in the PCI Express configuration space. The local host should program these attributes

before setting the config-ready bit in the PCI Express configuration space so that the RC host reads the

correct information during enumeration. These registers are used only in EP mode.

14.4.7.1 PCI Express BAR Size Low Configuration Register (PEX_BAR_SIZEL)

PEX_BAR_SIZEL, shown in Figure 14-89, configures the size of the 32-bit address windows and low

portion of the 64-bit address windows by setting the mask value for the base address registers (BAR) in

the PCI Express configuration space. The specific PCI Express BAR is selected by the PCI Express BAR

select configuration register (PEX_BAR_SEL). Before programming this register, the PEX_BAR_SEL

only in EP mode.

NOTE

Because the CSB address space of the device is limited to 4 Gigabytes, the

high portion of the 64-bit address window mask value is always set to all

ones (0xFFFF_FFFF) to comply with the standard enumeration sequence.

Offset 0x4B0 Access: Mixed

31 10

— CFG_READY

Reset All zeros

Figure 14-88. PCI Express Configuration Ready Register (PEX_CFG_READY)

Table 14-86. PEX_CFG_READY Fields Description

Bits Name Description

31–1 — Reserved

0 CFG_READY Configuration ready

1 The transaction layer accepts inbound configuration requests.

0 The transaction layer responds to all inbound configuration requests with retry (CRS)