Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-70 Freescale Semiconductor
upstream device. This register has to be programmed before setting the config-ready bit in the PCI Express
configuration ready register so that the host reads the correct information during enumeration.
The fields of the PCI Express link capabilities update register are described in Table 14-84.
Offset 0x480 Access: R/W
31 14 13 11 10 8 7 6 5 0
R
— L1EXL L0SEXL ASPM MLW
W
Reset000000000000000000111101 0 1 000001
Figure 14-86. PCI Express Link Capabilities Update Register
Table 14-84. PCI Express Link Capabilities Update Register Fields Description
Bits Name Description
31–14 — Reserved
13–11 L1EXL L1 Exit Latency for the given PCI Express Link. The value reported indicates the length of
time this port requires to complete transition from L1 to L0. Defined encodings are:
000b Less than 1 s
001b 1 s to less than 2 s
010b 2 s to less than 4 s
011b 4 s to less than 8 s
100b 8 s to less than 16 s
101b 16 s to less than 32 s
110b 32 s to 64 s
111b More than 64 s
Note: Exit latencies may be influenced by PCI-Express reference clock configuration
depending upon whether a component uses a common or separate reference clock.
10–8 L0SEXL L0s Exit Latency for the given PCI Express Link. The value reported indicates the length of
time this port requires to complete transition from L0s to L0. Defined encodings are:
000b Less than 64 ns
001b 64 ns to less than 128 ns
010b 128 ns to less than 256 ns
011b 256 ns to less than 512 ns
100b 512 ns to less than 1s
101b 1 s to less than 2 s
110b 2 s to 4 s
111b More than 4 s
Note: Exit latencies may be influenced by PCI Express reference clock configuration
depending upon whether a component uses a common or separate reference clock.
This field is automatically updated to a new value if the common clock configuration
bit in config space is set by host.
7–6 ASPM ASPM Support. Indicates the level of ASPM supported on the given PCI Express Link.
Defined encodings are:
00b Reserved
01b L0s Entry Supported
10b Reserved
11b Reserved (L0s and L1 not supported by this device)
5–0 MLW Maximum Link Width of the given PCI Express Link. Defined encodings are:
000001b 1
Other: Reserved