Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-69
The fields of the PCI Express Device Capabilities Update Register are described in Table 14-83.
14.4.6.10 PCI Express Link Capabilities Update Register
(PEX_LINKCAP_UPDATE)
The PCI Express link capabilities update register shown in Figure 14-86 is used to set the values to the PCI
Express link capabilities register in the PCI Express configuration header (offset 0x58). It can be used
when the device is configured as an End Point to make the correct link information available to the
Offset 0x47C Access: R/W
31 14 13 12 11 9 8 6 5 4 3 2 0
R
— PIP AIP APB L1AL L0SAL MPLS
W
Reset00000000000000000 0 0 0 000000000000
Figure 14-85. PCI Express Device Capabilities Update Register
Table 14-83. PCI Express Device Capabilities Update Register Fields Description
Bits Name Description
31–15 — Reserved
14 PIP Power Indicator Present
13 AIP Attention Indicator Present
12 APB Attention Button Present
11–9 L1AL Endpoint L1 Acceptable Latency. This field indicates the acceptable latency that an Endpoint can
withstand due to the transition from L1 state to the L0 state. Defined encodings are:
000b Less than 1us
001b 1 s to less than 2 s
010b 2 s to less than 4 s
011b 4 s to less than 8 s
100b 8 s to less than 16 s
101b 16 s to less than 32 s
110b 32 s-64 ìs
111b More than 64 s
8–6 L0SAL Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an Endpoint
can withstand due to the transition from L0s state to the L0 state. Defined encodings are:
000b Less than 64 ns
001b 64 ns to less than 128 ns
010b 128 ns to less than 256 ns
011b 256 ns to less than 512 ns
100b 512 ns to less than 1 s
101b 1 s to less than 2 s
110b 2 s-4 s
111b More than 4 s
5 — Reserved (Extended Tag Field Supported). Must be set to 0b.
4–3 — Reserved (Phantom Functions Supported). Must be set to 00b.
2–0 MPLS Max Payload Size Supported. Must be set to 000b (128bytes)