Information
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-68 Freescale Semiconductor
Table 14-81 describes the PCI Express ASPM request timer register fields.
14.4.6.8 PCI Express Subsystem Vendor ID Update Register
(PEX_SSVID_UPDATE)
The PCI Express subsystem vendor ID update register (PEX_SSVID_UPDATE) shown in Figure 14-84 is
used to configure the subsystem vendor ID and subsystem ID fields of the configuration header (offset
0x2C) for End Point devices. This register has to be programmed before setting the config-ready bit in the
PCI express configuration ready register so that the host reads the correct information during enumeration.
14.4.6.9 PCI Express Device Capabilities Update Register
(PEX_DEVCAP_UPDATE)
The PCI Express device capabilities update register shown in Figure 14-85 is used to set the values to the
PCI Express device capabilities register in the PCI Express configuration header (offset 0x50). It can be
used when the device is configured as an End Point to make the correct device information available to the
upstream device. This register has to be programmed before setting the config-ready bit in the PCI Express
configuration ready register so that the host reads the correct information during enumeration.
Table 14-81. PCI Express ASPM Request Timer Register Fields Description
Bits Name Description
31–13 — Reserved
12–0 ASPML1TMR ASPM L1 request timer value. This is the time-out interval after sending NAK message, before a
new ASPM L1 request from a downstream device is treated as a new ASPM L1 entry request.
For example, if the upstream device rejects an ASPM L1 entry request from a downstream
device with ASPM NAK message, the next ASPM L1 entry request from downstream device will
be entertained only after this timeout interval or only after the Rx link of the downstream port
enters L0s state. This value is specified in terms of system clock cycles (CSB clock/
PCIEXPnCM). This value can be calculated as [Time in microseconds SYSTEM_CLK in MHz].
For example 9.5[s] 125[MHz] = 1187 (0x4A3). This register is used only in RC mode.
Offset 0x478 (EP mode only) Access: R/W
31 16 15 0
R
SSID SSVID
W
Reset All zeros
Figure 14-84. PCI Express Subsystem Vendor ID Update Register (PEX_SSVID_UPDATE)
Table 14-82. PEX_SSVID_UPDATE Fields Description
Bits Name Description
31–16 SSID Subsystem ID
15–0 SSVID Subsystem Vendor ID