Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-67
14.4.6.6 PCI Express PME Time-Out Register (PEX_PME_TIMEOUT)
(EP Mode Only)
PEX_PME_TIMEOUT, shown in Figure 14-82, is used to program the time-out value that the controller
uses before re-sending a PME message to the host. If PME is requested by a function and the host does not
clear the associated PME_STAT bit even after this time-out has expired, the PME message is sent again to
the host by the PCI Express controller. This register is supported only for EP mode.
The fields of PEX_PME_TIMEOUT are described in Table 14-79.
14.4.6.7 PCI Express ASPM Request Timer Register (PEX_ASPM_REQTMR)
The PCI Express ASPM request timer register (PEX_ASPM_REQTMR) shown in Figure 14-83 is used
to program the time interval between two ASPM L1 entry requests from a downstream device before
deciding that the second request is a new request. This timer value is required because, if the upstream port
rejects an ASPM L1 entry request by sending a NAK message, the L1 request DLLPs continue to be
received for some more time due to the link and processing latency involved before downstream device
processes the NAK msg and stops the request. Meanwhile, these request DLLPs should not be considered
as a new L1 entry request and responded with Ack DLLP. For more details refer to the PCI Express Base
Specification Rev 1.0a errata, C7. ASPM & PCI-PM L1.
The fields of the PCI Express ASPM request timer register are described in Table 14-81.
Offset 0x454 (EP mode only) Access: Mixed
31 26 25 0
R
—PME_TIMEOUT
W
Reset00000000111111010100101111000000
Figure 14-82. PCI Express PME Time-Out Register (PEX_PME_TIMEOUT)
Table 14-80. PEX_PME_TIMEOUT Fields Description
Bits Name Description
31–26 — Reserved
25–0 PME_TIMEOUT The interval before PME messages are resent by the controller if the PME_STAT bit in the PCI
Express power management status and control register (offset 0x048) is not cleared by the host.
The value for PME_TIMEOUT is specified in terms of PCI Express controller core clock cycles.
The value is calculated as:
Time (in µsec) × PCI Express controller core clock frequency (in MHz)
The minimum time value is 100 msec
Offset 0x45C (RC mode only) Access: R/W
31 13 12 0
R
— ASPML1TMR
W
Reset00000000000000000000011000101001
Figure 14-83. PCI Express ASPM Request Timer Register