Information
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-66 Freescale Semiconductor
Table 14-78 describes the PEX_GCLK_RATIO fields.
14.4.6.5 PCI Express Power Management Timer Register (PEX_PM_TIMER)
PEX_PM_TIMER, shown in Figure 14-81, is used to program the time-in values for entering L0s and L1
power management states.
The fields of the PEX_PM_TIMER are described in Table 14-79.
Offset 0x440 Access: Mixed
31 65 0
R
— CLKRN
W
Reset000000000000000000000 0 0 000010000
Figure 14-80. PCI Express Core Clock Ratio Register (PEX_GCLK_RATIO)
Table 14-78. PEX_GCLK_RATIO Fields Description
Bits Name Description
31–6 — Reserved
5–0 CLKRN Clock Ratio Numerator. The numerator of the ratio of the actual PCI Express controller core clock used
to the maximal core clock of 125 MHz. These bits should be programmed only when the PCI Express
controller is required to run at a clock frequency other than the maximum.
The denominator of the ratio is fixed at 16. The default value of this register is 0x10 (16 decimal), which
corresponds to a ratio of 1:1 (or 16/16). For example, if the PCI Express controller clock is 62 MHz, the
ratio of the clocks is 1:2 (equivalent to 8/16). Therefore these bits should be programmed to a value of
8, or 0x0000_0008.
Offset 0x450 Access: Mixed
31 24 23 12 11 0
R —
L1_WAIT_PERIOD L0s_TIME_IN
W
Reset
000000000000101001100011111001
00
Figure 14-81. PCI Express Power Management Timer Register (PEX_PM_TIMER)
Table 14-79. PEX_PM_TIMER Fields Description
Bits Name Description
31–24 — Reserved
23–12 L1_WAIT_PERIOD Wait period (in PCI Express controller core clock cycles) before entering L1 power state after all
functions are in a non-D0 power state. The value is calculated as:
Time (in µsec) × PCI Express controller core clock frequency (in MHz)
The time value must be less than 2 µsec
11–0 L0s_TIME_IN Time in value (in PCI Express controller core clock cycles) for entering L0s power state. The
value is calculated as:
Time (in µsec) × PCI Express controller core clock frequency (in MHz)
The maximum time value is 7 µsec