Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-65
Table 14-77 describes PCI Express N_FTS control register fields.
14.4.6.4 PCI Express Controller Core Clock Ratio Register (PEX_GCLK_RATIO)
The PCI Express controller core clock ratio register, shown in Figure 14-80, is used to program the ratio
of the actual PCI Express controller core clock (csb_clk divided according to SCCR[PCIEXPnCM])
frequency to the maximum possible controller core frequency (133 MHz). Changing the default value of
this register is required only when a PCI Express controller core clock frequency is different than its
maximum.
This ratio will be used by the PCI Express controller only to calculate the actual timer values to be used
for Ack Latency and Replay timeout values. These two timer values have to dynamically change based on
the negotiated link-width and max-payload size. The default value by itself is not enough for these two
timers. By programming the clock ratio in this register, the calculation is automatically adjusted by
hardware. Note that other timer registers in the PCI Express controller may still have to be programmed
to a new value based on the actual controller core clock used in the specific application.
NOTE
The default PCI Express controller core clock is csb_clk
(SCCR[PCIEXPnCM] = 0b01).
Table 14-77. PCI Express ACK Replay Timeout Register Fields Description
Bits Name Description
31–27 — Reserved
26–13 ACKRTV Ack Replay Timeout Value. Timeout value to wait for reception of ACK DLLP from the link side by
the DLL before re-transmitting TLPs. The protocol specifies this value in symbol times for various
combinations of max-payload size and negotiated link width. The value programmed into this field
should be in terms of system clock cycles number, and can be calculated as:
• REPLAY_TIMER_TIMEOUT—Timeout value for the replay timer, specified in symbol times.
• Rx_L0s_Adjustment—The time required by the component’s receive circuits to exit from L0s to L0
specified in symbol times.
• SYSTEM_CLOCK—The PCI Express controller system clock, specified in MHz.
Note: The “250” denominator represent the frequency of a symbol (250 MHz).
12–0 ACKLTV Ack Latency Timeout Value. Timeout value to force transmission of ACK DLLP by the DLL after a
TLP is received. The protocol specifies this value in symbol times for various combinations of
max-payload size & negotiated link width. The value programmed into this field should be in terms of
system clock cycles number, and can be calculated as:
• ACK_LATENCY_TIMEOUT—Timeout value to force transmission of ACK DLLP, specified in symbol
times.
• Tx_L0s_Adjustment—The time required for the Transmitter to exit L0s, specified in symbol times.
• SYSTEM_CLOCK—The PCI Express controller system clock, specified in MHz.
Note: The “250” denominator represent the frequency of a symbol (250 MHz).
REPLAY_TIMER_TIMEOUT Rx_L0s_Adjustment+SYSTEM_CLOCK
250
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ACK_LATENCY_TIEMOUT Tx_L0s_Adjustment+SYSTEM_CLOCK
250
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