Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-63
14.4.6.2 PCI Express N_FTS Control Register (PEX_NFTS_CTRL)
The PCI Express N_FTS Control Register, shown in Figure 14-78, is used to set the N_FTS value that is
advertised by the PCI Express controller during link training. It is preferable to set it before the PCI
Express core internal reset is negated. If this value is changed after the link is up, the new value will take
effect during the next link training. The N_FTS value is should be set according to the L0s exit latency of
0F Configuration lane number wait (2) 36 Recovery cfg (1)
10 Configuration lane number wait (3) 37 Recovery idle (0)
11 Configuration lane number accept 38 Recovery idle (1)
12 Configuration complete (0) 39 Recovery to configuration
13 Configuration complete (1) 3A Recovery cfg to configuration
14 Configuration idle (0) 3F L0 no training
15 Configuration idle (1) 7F Detect quiet EI
16 L0 49 Configuration link width start—RC
17 TX L0; RX L0s entry 4A Configuration link width accept—RC
18 TX L0; RX L0s idle 4B Configuration lane number wait—RC
19 TX L0; RX L0s fast training sequence (FTS) 4C Configuration lane number accept—RC
1A TX L0s entry (0); RX L0 60 Loopback slave active (0)
1B TX L0s entry (0); RX L0s idle 61 Loopback slave active (1)
1C TX L0s entry (0); RX L0s FTS 62 Loopback slave exit
1D TX L0s entry (1); RX L0 68 Hot reset (0)
1E TX L0s entry (1); RX L0s idle 69 Hot reset (1)
1F TX L0s entry (1); RX L0s FTS 6A Hot reset (0)—RC
20 TX L0s idle; RX L0 6B Hot reset (1)—RC
21 TX L0s idle; RX L0s entry 75 Disabled (0)
22 TX L0s idle; RX L0s idle 71 Disabled (1)
23 TX L0s idle; RX L0s FTS 72 Disabled (2)
24 TX L0s FTS; RX L0 73 Disabled (3)
25 TX L0s FTS; RX L0s entry 74 Disabled (4)
26 TX L0s FTS; RX L0s idle 78 L0 to L1/L2—RC
Table 14-75. PEX_LTSSM_STAT Status Codes (continued)
Status Code
(Hex)
LTSSM State Description
Status Code
(Hex)
LTSSM State Description