Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
viii Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
8.5.21 System Error Force Register (SERFR)...................................................................... 8-29
8.5.22 System Critical Interrupt Vector Register (SCVCR)................................................. 8-30
8.5.23 System Management Interrupt Vector Register (SMVCR) ....................................... 8-30
8.6 Functional Description................................................................................................... 8-31
8.6.1 Interrupt Types........................................................................................................... 8-31
8.6.2 Interrupt Configuration.............................................................................................. 8-32
8.6.3 Internal Interrupts Group Relative Priority................................................................ 8-33
8.6.4 Mixed Interrupts Group Relative Priority.................................................................. 8-33
8.6.5 Highest Priority Interrupt........................................................................................... 8-34
8.6.6 Interrupt Source Priorities.......................................................................................... 8-34
8.6.7 Masking Interrupt Sources......................................................................................... 8-38
8.6.8 Interrupt Vector Generation and Calculation............................................................. 8-39
8.6.9 Machine Check Interrupts.......................................................................................... 8-39
8.7 Message Shared Interrupts............................................................................................. 8-40
8.7.1 Memory Map/Register Definition ............................................................................. 8-40
8.7.2 Message Shared Registers ......................................................................................... 8-40
Chapter 9
DDR Memory Controller
9.1 Introduction...................................................................................................................... 9-1
9.2 Features............................................................................................................................ 9-2
9.2.1 Modes of Operation ..................................................................................................... 9-3
9.3 External Signal Descriptions ........................................................................................... 9-3
9.3.1 Signals Overview......................................................................................................... 9-3
9.3.2 Detailed Signal Descriptions ....................................................................................... 9-6
9.4 Memory Map/Register Definition ................................................................................... 9-9
9.4.1 Register Descriptions................................................................................................. 9-10
9.5 Functional Description................................................................................................... 9-38
9.5.1 DDR SDRAM Interface Operation............................................................................ 9-42
9.5.2 DDR SDRAM Address Multiplexing........................................................................ 9-43
9.5.3 JEDEC Standard DDR SDRAM Interface Commands ............................................. 9-45
9.5.4 DDR SDRAM Interface Timing................................................................................ 9-47
9.5.5 DDR SDRAM Mode-Set Command Timing............................................................. 9-51
9.5.6 DDR SDRAM Registered DIMM Mode................................................................... 9-51
9.5.7 DDR SDRAM Write Timing Adjustments................................................................ 9-52
9.5.8 DDR SDRAM Refresh .............................................................................................. 9-53
9.5.9 DDR Data Beat Ordering........................................................................................... 9-56
9.5.10 Page Mode and Logical Bank Retention ................................................................... 9-57
9.5.11 Error Checking and Correcting (ECC) ...................................................................... 9-58
9.5.12 Error Management..................................................................................................... 9-60