Information

PCI Express Interface Controller

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 14-61

Table 14-72 describes the PCI Express root error command register fields.

14.4.5.11 PCI Express Error Source Identification Register

The error source identification register shown in Figure 14-76 identifies the source (Requestor ID) of first

correctable and uncorrectable (non-fatal/fatal) errors reported in the root error status register. This register

is relevant for RC only.

Table 14-73 describes the PCI Express root source identification register fields.

Table 14-72. PCI Express Root Error Status Register Fields Description

Bits Name Description

31–27 AEIMN Advanced error interrupt message number.

26–7 — Reserved

6 FEMR Fatal error messages received.

5 NFEMR Non-fatal error messages received.

4 FUF First uncorrectable fatal.

3 MEFNFR Multiple ERR_FATAL/NONFATAL received.

2 EFNFR ERR_FATAL/NONFATAL received.

1 MECR Multiple ERR_COR received.

0 ECR ERR_COR received.

Offset 0x134 Access: Read-only

31 16 15 2 1 0

R ERR_FATAL/NONFATAL Source ID ERR_COR Source ID

Reset All zeros

Figure 14-76. PCI Express Error Source Identification Register

Table 14-73. PCI Express Error Source Identification Register Fields Description

Bits Name Description

31–16 ERR_FATAL/NONFATAL

Source ID

ERR_FATAL/NONFATAL Source Identification. Loaded with the Requestor ID

indicated in the received ERR_FATAL or ERR_NONFATAL Message when the

ERR_FATAL/NONFATAL Received register is not already set.

15–0 ERR_COR Source ID Correctable Error Source Identification. Loaded with the Requestor ID indicated in the

received ERR_COR Message when the ERR_COR Received register is not already

set.