Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-60 Freescale Semiconductor
14.4.5.9 PCI Express Root Error Command Register
The PCI Express root error command register is shown in Figure 14-74.
Table 14-71 describes the PCI Express root error command register fields.
14.4.5.10 PCI Express Root Error Status Register
The PCI Express root error status register is shown in Figure 14-75.
Offset 0x12C Access: Read/Write
31 16
R
—
W
Reset All zeros
15 32 1 0
R
— FERE NFERE CERE
W
Reset All zeros
Figure 14-74. PCI Express Root Error Command Register
Table 14-71. PCI Express Root Error Command Register Fields Description
Bits Name Description
31–3 — Reserved
2 FERE Fatal error reporting enable.
1 NFERE Non-fatal error reporting enable
0 CERE Correctable error reporting enable
Offset 0x130 Access: Mixed
31 27 26 16
R AEIMN
—
W
Reset All zeros
15 7 6 5 4 3 2 1 0
R
—
FEMR NFEMR FUF MEFNFR EFNFR MECR ECR
W w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 14-75. PCI Express Root Error Status Register