Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-59
Table 14-70 describes the PCI Express header log register fields.
Offset 0x11C Access: Read-only
31 24 23 16 15 8 7 0
R Byte 0 Byte 1 Byte 2 Byte 3
W
Reset All zeros
Offset 0x120 Access: Read-only
31 24 23 16 15 8 7 0
R Byte 4 Byte 5 Byte 6 Byte 7
W
Reset All zeros
Offset 0x124 Access: Read-only
31 24 23 16 15 8 7 0
R Byte 8 Byte 9 Byte A Byte B
W
Reset All zeros
Offset 0x128 Access: Read-only
31 24 23 16 15 8 7 0
R Byte C Byte D Byte E Byte F
W
Reset All zeros
Figure 14-73. PCI Express Header Log Register
Table 14-70. PCI Express Header Log Register Fields Description
Bits Name Description
127–0 Header Log Header of TLP associated with error.