Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-58 Freescale Semiconductor
14.4.5.7 PCI Express Advanced Error Capabilities and Control Register
The PCI Express advanced error capabilities and control register is shown in Figure 14-72.
Table 14-69 describes the PCI Express advanced error capabilities and control register fields.
14.4.5.8 PCI Express Header Log Register
The PCI Express header log register is shown in Figure 14-73.
5–1 — Reserved
0 RXEM Receiver error mask
Offset 0x118 Access: Mixed
31 16
R
—
W
Reset0000000 0 0 0 0 0 0 0 0 0
15 987654 0
R
— ECRCCE
ECRCCC
ECRCGE
ECRCGC First Error Pointer
W
Reset0000000 0 1 0 1 0 0 0 0 0
Figure 14-72. PCI Express Advanced Error Capabilities and Control Register
Table 14-69. PCI Express Advanced Error Capabilities and Control Register Fields Description
Bits Name Description
31–9 — Reserved
8 ECRCCE ECRC checking enable. Set this bit to enable ECRC checking.
7 ECRCCC ECRC checking capable. Status bit indicates if this capability has been enabled.
0 ECRC checking capability is disabled.
1 ECRC checking capability is enabled.
6 ECRCGE ECRC generation enable. Set this bit to enable ECRC generation.
5 ECRCGC ECRC generation capable. Status bit indicates if this capability has been enabled.
0 ECRC generation capability is disabled.
1 ECRC generation capability is enabled.
4–0 First Error Pointer First error pointer. Identifies the bit position of the first error reported in uncorrectable error
status register, Section 14.4.5.2, “PCI Express Uncorrectable Error Status Register.”
Table 14-68. PCI Express Correctable Error Mask Register Fields Description (continued)
Bits Name Description