Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-57
Table 14-67 describes the PCI Express correctable error status register fields.
14.4.5.6 PCI Express Correctable Error Mask Register
The PCI Express correctable error mask register is shown in Figure 14-71. An error is masked if the
corresponding mask bit in this register is set.
Table 14-68 describes the PCI Express correctable error mask register fields.
Table 14-67. PCI Express Correctable Error Status Register Fields Description
Bits Name Description
31–13 — Reserved
12 RTTO Replay timer time-out status
11–9 — Reserved
8 RNR REPLAY_NUM rollover status
7 BDLLP Bad DLLP status
6 BTLP Bad TLP status
5–1 — Reserved
0 RXE Receiver error status
Offset 0x114 Access: Read/Write
31 16
R
—
W
Reset All zeros
15 13 12 11 9 8 7 6 5 1 0
R
— RTTOM — RNRM BDLLPM BTLPM — RXEM
W
Reset All zeros
Figure 14-71. PCI Express Correctable Error Mask Register
Table 14-68. PCI Express Correctable Error Mask Register Fields Description
Bits Name Description
31–13 — Reserved
12 RTTOM Replay timer timeout mask
11–9 — Reserved
8 RNRM REPLAY_NUM rollover mask
7 BDLLPM Bad DLLP mask
6 BTLPM Bad TLP mask