Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-56 Freescale Semiconductor
Table 14-66 describes the PCI Express uncorrectable error severity register fields.
14.4.5.5 PCI Express Correctable Error Status Register
The PCI Express correctable error status register is shown in Figure 14-70. When an individual error status
bit of this read-only register is set, it indicates that this particular error has occurred.
Table 14-66. PCI Express Uncorrectable Error Severity Register Fields Description
Bits Name Description
31–21 — Reserved
20 URES Unsupported request error severity
19 ECRCES ECRC error severity
18 MTLPS Malformed TLP severity
17 RXOS Receiver overflow severity
16 UCS Unexpected completion severity
15 CAS Completer abort severity
14 CTOS Completion timeout severity
13 FCPES Flow control protocol error severity
12 PTLPS Poisoned TLP severity
11–5 — Reserved
4 DLPES Data link protocol error severity
3–1 — Reserved
0 TES Training error severity
Offset 0x110 Access: w1c
31 16
R
—
W
Reset All zeros
15 13 12 11 9 8 7 6 5 1 0
R
—
RTTO
—
RNR BDLLP BTLP
—
RxE
W w1c w1c w1c w1c w1c
Reset All zeros
Figure 14-70. PCI Express Correctable Error Status Register