Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-55
Table 14-65 describes the PCI Express uncorrectable error mask register fields.
14.4.5.4 PCI Express Uncorrectable Error Severity Register
The PCI Express uncorrectable error severity register is shown in Figure 14-69. An error is reported as
fatal if the corresponding severity bit is set; otherwise it is reported as non-fatal.
Table 14-65. PCI Express Uncorrectable Error Mask Register Fields Description
Bits Name Description
31–21 — Reserved
20 UREM Unsupported request error mask
19 ECRCEM ECRC error mask
18 MTLPM Malformed TLP mask
17 RXOM Receiver overflow mask
16 UCM Unexpected completion mask
15 CAM Completer abort mask
14 CTOM Completion timeout mask
13 FCPEM Flow control protocol error mask
12 PTLPM Poisoned TLP mask
11–5 — Reserved
4 DLPEM Data link protocol error mask
3–1 — Reserved
0 TEM Training error mask
Offset 0x10C Access: Read/Write
31 21 20 19 18 17 16
R
— URES ECRCES MTLPS RXOS UCS
W
Reset0 0 0 0 0000000 0 0 1 1 0
15 14 13 12 11 5 4 3 1 0
R
CAS CTOS FCPES PTLPS — DLPES — TES
W
Reset0 0 1 0 0000000 1 0 0 0 0
Figure 14-69. PCI Express Uncorrectable Error Severity Register